Available courses

FAU teams regularly participate at the Student Cluster Competitions, often as the only German team. University students build their own supercomputers for a live face-off to see whose is the fastest.  The students not only need to build, install, and maintenance their own cluster system, but most importantly need to run both HPC-related benchmarks and given real-word, scientific workloads within a certain power limit, and the team with the highest-performing system wins.

In this course, the students will prepare for the competition, e.g., writing the submission to be accepted for participation, get hands-on experience on cluster hardware for learning system administration skills, benchmarking, and running applications on HPC systems. It is a 10 ECTS course and runs throughout the summer term 2025. For all students participating in-person in the competition, the course runs until November 2025.

In all modern HPC systems, the compute node is where code is executed and "performance is generated." Hence, this is where a deep understanding of the performance issues of any application must start. At first glance, computer architecture appears extremely intricate, making it next to impossible to derive general rules for good performance. However, on closer inspection it turns out that there is a surprisingly small number of guiding principles which govern most of the performance behavior of HPC codes. This online tutorial wants to convey those components of compute node architecture that are most relevant for performance in HPC. We start with the core level and cover code execution via pipelining and out-of-order processing, Single Instruction Multiple Data (SIMD), and Simultaneous Multi-Threading (SMT). Advancing through the memory hierarchy, we look at cache hierarchies, main memory, and cache-coherent non-uniform memory (ccNUMA) architecture. The commonalities and differences between CPUs and GPUs are clearly described. Using simple compute kernels from computational science, we show how architectural features interact with code. We also introduce the Roofline performance model as a simple way to formulate quantitative performance expectations, compare them with observations, and derive possible optimizations. Simple performance tools are introduced that favor insight instead of automation. To make this online event interactive, several online quizzes are interspersed with lectures. Participants can also solve exercise problems using H5P online content and our interactive "Layer Condition Calculator" for stencil codes.

This course, a collaboration of the Erlangen National High Performance Computing Center (NHR@FAU) and the Leibniz Supercomputing Center (LRZ), is targeted at students and scientists with interest in programming modern HPC hardware, specifically the large scale parallel computing systems available in Jülich, Stuttgart and Munich but also smaller clusters.

This course teaches performance engineering approaches on the compute node level. "Performance engineering" as we define it is more than employing tools to identify hotspots and bottlenecks. It is about developing a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. Once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of optimizations can often be predicted. We introduce a "holistic" node-level performance engineering strategy and apply it to different algorithms from computational science.


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