PTfS22: Assignment 2: Core performance, SIMD, cache lines (due May 20 11:59 p.m.)

Opened: Monday, 9 May 2022, 12:00 AM

Due: Saturday, 21 May 2022, 12:00 AM

Another triad code. (20 credits) Calculate the maximum achievable in-core performance \( P_\max \) of the AVX-vectorized double-precision STREAM triad on a Cascade Lake SP core at 2.3 GHz. The STREAM triad kernel is a[i] = b[i] + s * c[i]. What fraction of the peak DP performance can be achieved (theoretically)? Also calculate \( P_\max \) for the AVX-512 and scalar variants.
Pipelines and SIMD units. (50 credits) One way to increase the peak performance of a microprocessor is to use wider SIMD units and registers, just as Intel did when going from SSE (16 byte) to AVX (32 byte). 64-byte SIMD or AVX512 registers are now available in the "Xeon Skylake-X" and later architectures. Consider the following loop (a scalar product) on a modern processor core:
```
double s=0.0;
double a[N],b[N];
// ... initialization omitted
for(i=0; i<N; ++i) 
 s = s + a[i] * b[i];
```
The add (multiply) instruction has a latency of three (five) cycles and a maximum throughput of one per cycle. The load instruction has a latency of four cycles (if the data is in L1 cache) and a maximum throughput of one per cycle.

(a) Assuming that the compiler applies no unrolling and no SIMD vectorization, calculate the maximum possible performance of the loop in Flops/cycle if the data comes from the L1 cache.
(b) Calculate the performance to expect at N=8.
(c) Now assume that the compiler can SIMD-vectorize the loop with AVX, but does no unrolling beyond that. Also assume that adding up the four slots of an AVX register takes eight additional cycles. Calculate how this changes the predictions from (a) and (b). How would the numbers change for 8-wide SIMD units (64-byte registers)?
(d) Now assume that the compiler performs a 2-way modulo unrolling of the loop, on top of AVX. Calculate the maximum expected performance with AVX if the data comes from the L1 cache. Would 4-way unrolling change anything? Why (not)?
Strided access. (30 credits) Write a benchmark code for the double-precision "STREAM triad" kernel and modify it so that only each Mth element is used:
```
for(i=0; i<N; i+=M) { a[i] = b[i] + s * d[i]; }
```
This is called a "strided triad" with stride M. Plot the performance of this loop versus M∈{1,2,4,8} for N=4x10⁶ and explain the change in performance with growing M. What happens if you increase M even further? Choose strides as M=8*1.2ⁿ, with n a positive integer and M<=10⁵. Explain why this behavior is expected.