Assignment 2: Loop kernels galore!

• Clock frequency of 2.05 GHz
• 126 cores

• The new, still undisclosed "ShmAVX-1024" instruction set (1024-bit wide SIMD registers); each core is capable of retiring one full-width double-precision FMA instructions per cycle, but the clock speed is reduced by 10% from the base value if a loop with such "hot code" is executed.

  (a) (10 crd) Calculate the theoretical double-precision floating-point peak performance of the chip in TFlop/s. You may assume that the FMA SIMD units are fully parallel, i.e., the computations across the SIMD lanes are done concurrently.
  (b) (20 crd) Each core has also a Load/Store unit, which can execute one full-width SIMD Load or one full-width SIMD Store per cycle. Consider the following code: 
  
  

          double a[...],b[...];
          double s=0.0, t=1.234;
          // a[] and b[] contain sensible data
          for(int i=0; i<N; ++i) {
             s += a[i]*a[i];
             b[i] *= t;
          }
          

  Calculate the applicable peak performance P_max in Gflop/s for this code on all cores of the chip.
  
  

            NITER=1;
            do {
              // time measurement
              wct_start = getTimeStamp();

              // repeat measurement often enough
              for(k=0; k<NITER; ++k) {
                // This is the benchmark loop
                for(i=0; i<N; ++i) {
                 // put loop body here: a[i] = ...
                }
                // end of benchmark loop
                if(a[N/2]<0.) printf("%lf",a[N/2]); // prevent compiler from eliminating loop
              }
              wct_end = getTimeStamp();
              if(wct_end-wct_start>0.1) break; // at least 100 ms
              NITER = NITER*2;
            } while (1); 

            printf("Total walltime: %f, NITER: %d\n",wct_end-wct_start,NITER);