Assignment 4 Task 2

Assignment 4 Task 2

by Hassan Rady -
Number of replies: 1

Dear PTFS team,

Are we working on a single core level and the mentioned cache sizes are per core? Because I found that the transfer time from L2 to L1 is very insignificant and from L3 to L2 is even less which made me wonder, or this is what is expected from modern architectures.

Kind regards

Hassan Rady

In reply to Hassan Rady

Re: Assignment 4 Task 2

by Jan Laukemann -
Copied literally from the task description:

"This serial code is run on one core of a 24-core processor with cache sizes of 32 KiB (per-core L1), 1 MiB (per-core L2), and 27 MiB (shared L3)".

I believe this answers all your questions.