Dear PtfS Students,
In slide 6 of lecture set 5, the theoretical memory bandwidth of the chip is mentioned as 34.2 GB/s for 4 channels and 2.133 Gcy/s.
A student inquired in today's tutorial: why it's not 68.256 GB/s? Well, this is because the Haswell node was in Cluster-on-Die (CoD) mode (written in the lower yellow box in the middle). So effectively, there are only two channels per ccNUMA domain, hence only half the bandwidth.
Best regards,
Ayesha