Hi Isabella,
for Task 2 we have a simple (imaginary) microarchitecture which we could draw similar to the port model of a CPU on slide 21-23 of slide set 3a:
for Task 2 we have a simple (imaginary) microarchitecture which we could draw similar to the port model of a CPU on slide 21-23 of slide set 3a:
+-------------------------------------+
| Scheduler |
+-------------------------------------+
0 | 1 | 2 | 3 |
\/ \/ \/ \/
+-------+ +-------+ +------+ +------+
| ADD | | MULT | | LD | | ST |
+-------+ +-------+ +------+ +------+
You can see, the architecture supports superscalarity as multiple execution units (ADD, MULT, LD, ST) can run in parallel.
However, a single instruction still requires multiple pipeline steps, e.g., a single ADD instruction requires 6 cycles.
Each execution unit/port can retire 1 instruction per cycle at most (i.e., when the pipeline is constantly filled, they all have a throughput of 1 instr/cy), so the maximum throughput of our architecture is 4 instructions per cycle if all pipelines are always filled.
I hope this helps!