Hello all students,
I made a mistake in the solutions for Assignment 9. In task 3 c), the expected Schönauer Vector Triad L2 read to write data volume should be 4:1. This is because the automatic write-allocate evasion employed by our Intel "Ice Lake" chips on Fritz use cache line claim, not non-temporal stores. Since the cache line is claimed in the L3 cache, we observe a reduction in read data volume for MEM but not L2.
The corrected slides have been uploaded.
Best regards,
Dane