Hello,
may I know what it means by 'No overlap assumption does not hold on other architectures'?
Can anyone provide any hint?
Best regards
In intel processors,
In the memory hierarchy levels, for example, if we transfer data from L3 to L2 cache, L2 cache can't transfer data to L1 at the same time. we can say L2 cache is single ported.
In AMD, this is not the case.