Hi, I’d like to double-check two details about the PCIs in Q1 and Q2.
1st question:
In Q1 the statement says “The CPUs and GPUs of a node are connected via 2 PCIe interfaces each capable of transferring 32 GB s-¹ in each direction.”
Does “2 interfaces” mean
• two links for the whole node i.e. an aggregate 64 GB s-¹ up- and 64 GB s-¹ down for the node, or
• two links per chip, giving each device its own 64 GB s-¹.
2nd question:
In the formulas from the slides, for calculation of P_max we never take memory roofline into account, yet it was given in Q1, so do you expect us to use it there as well?
Thanks you in advance.
Thies