Question assignment 4, ex. 1b

Question assignment 4, ex. 1b

by Maximilian Jordan -
Number of replies: 1

Hello, 

I have a question on assignment 4, ex. 1b. The exercise states for the memory architecture that the "Maximum memory bandwidth [is] 110 Gbyte/s (independent of RD vs. WR, half duplex)". Does this mean that the memory bandwidth is 110Gbytes/s for both RD and WR but that we cannot split the bandwidth among both tasks because of half-duplex? Or does it mean, that the overall bandwidth is 110 Gbyte/s and that we can split it among both tasks, independently of the ration between LD and WR? 

Thanks in advance 

Maximilian Jordan

In reply to Maximilian Jordan

Re: Question assignment 4, ex. 1b

by Georg Hager -

Dear Maximilian,

"half-duplex" means that the memory bus can either be used to read or to write a cache line, but not both at the same time. However, it can alternate as required between the directions. Hence, the overall memory bandwidth is 110 GB/s, independent of the RD/WR ratio. You can use the 110 GB/s for read-only, for write-only, for copy (where 2/3 will be RD and 1/3 will be WR if write-allocate applies), etc.

Hope that helps,

Georg.