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Hi,
In Task 1, option b), we are expected to calculate the code balance (Bc). To do this, we first need to determine the data transfer volume.
In the slides, for the Haswell architecture, the value of 4.6 cycles per cache line for memory is calculated using the Load Only bandwidth, cache line size and clock frequency. However, for Ice Lake, the load only bandwidth and cache line size are not provided in the question. I was planning to use these values to calculate the transfer time to the next level of the memory hierarchy and then compute Bc-mem.
I’m wondering whether these values are actually needed for solving the task at all or if I might be overcomplicating it. If the information is indeed necessary, should we look them up from internet, or will you be providing the relevant hardware specs?
Thank you for your time and attention.
All the best and kind regards